#if !defined(_TGS_W32_COMMON_MATH_API_MATRIX_M_F_44_INL_)
#define _TGS_W32_COMMON_MATH_API_MATRIX_M_F_44_INL_
#pragma once
TgINLINE TgVOID M_CLI_F32_44( PCU_TgMAT_F32_44 ptmM0 )
{
ptmM0->m_atvRow[0].m_mData = TgKV_UNIT_X_F32_04.m_mData;
ptmM0->m_atvRow[1].m_mData = TgKV_UNIT_Y_F32_04.m_mData;
ptmM0->m_atvRow[2].m_mData = TgKV_UNIT_Z_F32_04.m_mData;
ptmM0->m_atvRow[3].m_mData = TgKV_UNIT_W_F32_04.m_mData;
};
TgINLINE TgVOID M_INV_F32_44( PCU_TgMAT_F32_44 ptmRet, CPCU_TgMAT_F32_44 ptmM1 )
{
M_INV_DET_F32_44( ptmRet, M_DET_F32_44( ptmM1 ), ptmM1 );
};
TgINLINE TgVEC_M_F32_04 M_TX_V4_F32_44( CPCU_TgMAT_F32_44 ptmM0, C_TgVEC_M_F32_04 tvX0 )
{
const register __m128 miXMM0 = _mm_unpacklo_ps( ptmM0->m_atvRow[0].m_mData, ptmM0->m_atvRow[1].m_mData );
const register __m128 miXMM1 = _mm_unpacklo_ps( ptmM0->m_atvRow[2].m_mData, ptmM0->m_atvRow[3].m_mData );
const register __m128 miXMM2 = _mm_unpackhi_ps( ptmM0->m_atvRow[0].m_mData, ptmM0->m_atvRow[1].m_mData );
const register __m128 miXMM3 = _mm_unpackhi_ps( ptmM0->m_atvRow[2].m_mData, ptmM0->m_atvRow[3].m_mData );
const register __m128 miXMM4 = _mm_movelh_ps( miXMM0, miXMM1 );
const register __m128 miXMM5 = _mm_movehl_ps( miXMM1, miXMM0 );
const register __m128 miXMM6 = _mm_movelh_ps( miXMM2, miXMM3 );
const register __m128 miXMM7 = _mm_movehl_ps( miXMM3, miXMM2 );
const register __m128 miXMM8 = _mm_mul_ps( _mm_shuffle_ps( tvX0, tvX0, 0x00 ), miXMM4 );
const register __m128 miXMM9 = _mm_mul_ps( _mm_shuffle_ps( tvX0, tvX0, 0x55 ), miXMM5 );
const register __m128 miXMMA = _mm_mul_ps( _mm_shuffle_ps( tvX0, tvX0, 0xAA ), miXMM6 );
const register __m128 miXMMB = _mm_mul_ps( _mm_shuffle_ps( tvX0, tvX0, 0xFF ), miXMM7 );
return (( _mm_add_ps( _mm_add_ps( miXMM8, miXMM9 ), _mm_add_ps( miXMMA, miXMMB ) ) ));
};
TgINLINE TgVEC_M_F32_04 M_GET_COL_0_V4_F32_44( CPCU_TgMAT_F32_44 ptmM0 )
{
register __m128 miXMM0 = _mm_shuffle_ps( ptmM0->m_atvRow[0].m_mData, ptmM0->m_atvRow[1].m_mData, 0x44 );
register __m128 miXMM1 = _mm_shuffle_ps( ptmM0->m_atvRow[2].m_mData, ptmM0->m_atvRow[3].m_mData, 0x44 );
return (( _mm_shuffle_ps( miXMM0, miXMM1, 0x88 ) ));
};
TgINLINE TgVEC_M_F32_04 M_GET_COL_1_V4_F32_44( CPCU_TgMAT_F32_44 ptmM0 )
{
register __m128 miXMM0 = _mm_shuffle_ps( ptmM0->m_atvRow[0].m_mData, ptmM0->m_atvRow[1].m_mData, 0x44 );
register __m128 miXMM1 = _mm_shuffle_ps( ptmM0->m_atvRow[2].m_mData, ptmM0->m_atvRow[3].m_mData, 0x44 );
return (( _mm_shuffle_ps( miXMM0, miXMM1, 0xDD ) ));
};
TgINLINE TgVEC_M_F32_04 M_GET_COL_2_V4_F32_44( CPCU_TgMAT_F32_44 ptmM0 )
{
register __m128 miXMM2 = _mm_shuffle_ps( ptmM0->m_atvRow[0].m_mData, ptmM0->m_atvRow[1].m_mData, 0xEE );
register __m128 miXMM3 = _mm_shuffle_ps( ptmM0->m_atvRow[2].m_mData, ptmM0->m_atvRow[3].m_mData, 0xEE );
return (( _mm_shuffle_ps( miXMM2, miXMM3, 0x88 ) ));
};
TgINLINE TgVEC_M_F32_04 M_GET_COL_3_V4_F32_44( CPCU_TgMAT_F32_44 ptmM0 )
{
register __m128 miXMM2 = _mm_shuffle_ps( ptmM0->m_atvRow[0].m_mData, ptmM0->m_atvRow[1].m_mData, 0xEE );
register __m128 miXMM3 = _mm_shuffle_ps( ptmM0->m_atvRow[2].m_mData, ptmM0->m_atvRow[3].m_mData, 0xEE );
return (( _mm_shuffle_ps( miXMM2, miXMM3, 0xDD ) ));
};
#endif